A standard Peripheral Component Interconnect (PCI) bus is generally known as a local parallel bus that allows expansion cards to be added into a single computer system. Examples of commercially available expansion cards with PCI bus interface are SCSI (data storage) cards, wireless LAN add-in cards, analog and digital TV tuner add-in cards, USB and FireWire controllers, Gigabit Ethernet add-in cards, etc. The PCI bus communicates with a single CPU or multiple CPUs of the computer system through a PCI-bridge controller. Several PCI bridges may exist in a computer system and couple a diversity of input/output (IO) devices to the multiple CPUs of the computer system.
The PCI bus standard uses an 8-bit address for addressing up to 256 possible PCI buses, each bus supports up to 32 devices (5-bit device number), each device contains up to 8 functions (3-bit function number). The 8-bit bus number, the 5-bit device number and the 3-bit function number, in short BDF hereinafter, form a routing identifier (ID) for the PCI bus subsystem. FIG. 1 shows a basic computer system containing two PCI buses. Two devices and a bridge are connected to the first bus (Bus 0), and three devices are connected to the second bus (Bus 1). The routing ID for each device starts with the bus number.
The PCI protocol is based around functions within a device which generates transactions. The requester generates a request transaction and the completer responds with a completion transaction. The completion is routed back to the requester by means of the requester's routing ID. Data are assembled in packets and moved across PCI bridges or switches. Each packet contains the requester ID (a 16-bit source address) and the destination ID (the completer address, which is identified by the 16-bit BDF). FIG. 2 illustrates an example of a request transaction originating from the root complex and a completion transaction from Device B.
PCI-Express (PCIe) is a modification of the standard PCI bus. It uses a point-to-point high-speed serial communication instead of a bus structure of the PCI bus. However, in order to maintain software compatibility, it is architected with the same PCI tree structured I/O interconnect topology. As the PCIe is a point-to-point interconnection, only one PCIe device can sit on a bus. Consequently, the number of supported devices drops to the number of buses. This architecture severely limits the number of devices that can exist in a PCI subsystem.
PCIe encodes transactions using a packet based protocol. Various types of packets such as memory read and write requests, IO read and write requests, message requests and completions are defined. A PCIe packet is shown in FIG. 3.
In the PCIe topology, Bus 0 denotes the device that connects the CPU and memory subsystem to the PCIe fabric. It may support one or more PCIe ports. For example, the root complex in FIG. 1 supports 2 devices and a bridge. Root complex (RC) transmits packets out of its ports and receives packets on its ports. A multi-port root complex may also route packets from one port to another port.
The root complex initializes with a bus number, device number and function number, referred to together as the bus-device-function (BDF) number, which are used to form a completer ID. The root complex BDF initializes to all 0s.
PCIe endpoints implement Type 0 PCI configuration headers and respond to configuration transactions as completers. Each endpoint is initialized with a device ID (requester ID or completer ID) which consists of a bus number, device number and function number. Endpoints are always device 0 on a bus.
Components and terminology used in a PCIe system are further described below. In the context of PCIe, a root complex is a component in a PCIe hierarchy that connects to the CPU and the memory subsystem on the upstream and one or more PCIe links on the downstream. That is, the root complex (RC) denotes the device that connects the CPU and memory subsystems to the PCIe fabric. A PCIe fabric encompasses all devices and links associated with an RC. A bridge connects two PCI buses. A switch consists of at least two or more logical PCI-to-PCI bridges with each bridge associated with a switch port. A port is the physical interface between a PCIe component and the PCIe link. A packet is information moved across an active PCIe link. An upstream port is a port that points in the direction of the RC. A downstream port is a port that points away from the RC. An endpoint is a device located at the downstream of the RC having one to eight functions. An endpoint is an upstream port. An RC port is a downstream port. A requester is a device that originates a transaction in the PCIe fabric. A completer is a device addressed by a requester.
A PCIe link is equivalent to a logical PCI bus, i.e., each link is assigned a bus number by the bus enumerating software. The first link associated with the RC is bus number 1. Bus 0 is an internal virtual bus within the RC. The internal bus within a switch that connects all the virtual bridges together is also numbered. FIG. 4 shows an example structure of a PCIe switch. A bus number is assigned to each port, upstream and downstream, (Bus 1, Bus 3, Bus 4, and Bus 5) as well as an internal bus (Bus 2) that connects the upstream port with the downstream ports. In order to maintain the PCI bridge topology, the PCIe switch allocates a bus number for each of its ports and its internal bus in this manner.
To get around the bus number limitation, two techniques are available: The non-transparent bridge (NTB) and the alternative routing interpretation (ARI).
A non-transparent bridge is a bridge that exposes a Type 0 control-and-status register (CSR) header on both sides and forwards transactions from one side to the other with address translation. Because it exposes a Type 0 CSR header, the bridge appears to be an endpoint to discovery and configuration software, eliminating potential discovery software conflicts. Since devices on one side of the bridge are not seen or exposed on the other side as in a conventional PCI bridge, the so designed bridge is called non-transparent bridge. Non-transparent bridges add expense and complication to the PCIe system and require higher layer applications to properly complete discovery and enumeration of a system.
Alternative routing interpretation (ARI) exploits the fact that, in PCI-Express, device numbers are always 0 for endpoints. It just extends the function number to 8 bits, replacing the device number. The main advantage of this is that existing bridges will continue to work as they use the bus number to route. The disadvantage is that the number of buses supported in the system is still a restriction in many PCI-Express architectures. So ARI does not increase the number of supported devices in a PCI-Express system, only the number of functions a device may support.
As the PCIe is a point-to-point connection, device numbers used previously in a PCI bus to identify the addressed device coupled to a PCI bus are not really useful anymore. The present invention proposes to use the entire 16 bits of the BDF as a system “function space”. This 16 bit expanded routing scheme is called the Universal Routing ID (URID). FIG. 5 shows the standard BDF is expanded to a 16-bit URID. The technique of using these numbers in a PCI-Express system is called Universal Routing. The URID will expand the current PCI and PCIe protocols to enable not maximum eight functions per device but 64K (65356) device functions to be connected to the PCIe fabric independent of how they are distributed to devices or upon buses throughout the system. As the result, the PCIe system is able to support tens of thousands of single-function devices. The foregoing description has been presented for purposes of illustration. Obvious modifications or variations are possible in light of the above teachings. For example, the routing identifier can be modified to span a plurality of identifier fields in a standard PCI/PCI-Express format.
In order to expand the existing PCI/PCIe routing capability, the present invention defines a field space in the PCIe packet, called URID capability segment. The URID capability segment can be located anywhere, but at a fixed location, in the PCIe packet, e.g., it can be located within the header, between the sequence number and the header, or preferably within the device configuration space in order to preserve the format of the PCIe packet. This field can be read from or written to by the enumeration software. Based on information contained in the URID capability segment, a URID capable bridge or switch can be configured to support new URID routing to tens of thousands single function devices.
The present invention provides a method for identifying devices capable of URID in a PCIe switched fabric. A PCIe fabric equipped with URID capable devices will be able to address tens of thousands of functions. Conventional PCIe switches will extend their routing table from 8-bit to 16-bit to accommodate the URID concept. A URID capability segment field will be added in the configuration space. The enumeration agent will parse (analyze) this field for identifying URID capable devices and configure the URID capability registers in the corresponding configuration space.
The present invention uses a portion of the current PCIe configuration space to implement additional features. In order to implement additional features, the invention defines a field in the PCIe configuration space called “URID capability segment”. All devices capable of URID must have this URID capability segment (FIG. 6).